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DATE
2003
IEEE
105views Hardware» more  DATE 2003»
14 years 25 days ago
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...
GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
ESE
2006
100views Database» more  ESE 2006»
13 years 7 months ago
An evaluation of combination strategies for test case selection
This paper presents results from a comparative evaluation of five combination strategies. Combination strategies are test case selection methods that combine "interesting&quo...
Mats Grindal, Birgitta Lindström, Jeff Offutt...
ISMB
1998
13 years 9 months ago
Sequence Assembly Validation by Multiple Restriction Digest Fragment Coverage Analysis
DNA sequence analysis depends on the accurate assembly of fragment reads for the determination of a consensus sequence. This report examines the possibility of analyzing multiple,...
Eric C. Rouchka, David J. States
AIS
2004
Springer
13 years 11 months ago
Timed I/O Test Sequences for Discrete Event Model Verification
Abstract. Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementatio...
Ki Jung Hong, Tag Gon Kim