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127
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DSD
2006
IEEE
93views Hardware» more  DSD 2006»
15 years 9 months ago
High-Level Decision Diagram based Fault Models for Targeting FSMs
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
Jaan Raik, Raimund Ubar, Taavi Viilukas
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
15 years 8 months ago
BISD: Scan-based Built-In self-diagnosis
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
Melanie Elm, Hans-Joachim Wunderlich
133
Voted
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
15 years 8 months ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
123
Voted
ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
15 years 7 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
148
Voted
SIGSOFT
2010
ACM
15 years 1 months ago
Bridging gaps between developers and testers in globally-distributed software development
One of the main challenges in distributed development is ensuring effective communication and coordination among the distributed teams. In this context, little attention has been ...
Mark Grechanik, James A. Jones, Alessandro Orso, A...