203 search results - page 11 / 41 » Test Generation and Fault Localization for Quantum Circuits |
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
ET
2002
13 years 7 months ago
2002
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
DFT
2002
IEEE
14 years 13 days ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...