A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction

−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test pattern generation algorithm show nearly 100% fault coverage for complex arithmetic logic circuits. Moreover we achieved 99.99% fault coverage applying this algorithm with a weighted random pattern generator to the LSIs (100-450 kgates) of Hitachi MP5800 mainframe computer.

• Type: Conference
• Year: 1998
• Where: ASPDAC
• Authors: Miyako Tandai, Takao Shinsha
• Keywords: ASPDAC 1998, Fault Coverage, Fault Identification Algorithm, Hardware, Pattern Generation Algorithm