203 search results - page 28 / 41 » Test Generation and Fault Localization for Quantum Circuits |
VLSID
1996
IEEE
13 years 11 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
VTS
1999
IEEE
13 years 11 months ago
1999
IEEE
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
Abstract— In this paper we study the testability of circuits derived from Binary Decision Diagrams (BDDs) under the bridging fault model. It is shown that testability can be form...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...