203 search results - page 40 / 41 » Test Generation and Fault Localization for Quantum Circuits |
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
BC
2008
13 years 7 months ago
2008
Abstract This paper presents a simple yet biologicallygrounded model for the neural control of Caenorhabditis elegans forward locomotion. We identify a minimal circuit within the C...
ITC
2003
IEEE
14 years 21 days ago
2003
IEEE
A scalable laser-based timing analysis technique we call laser assisted device alteration (LADA) is introduced for the rapid isolation and analysis of defect-free performance limi...
VLSID
2008
IEEE
14 years 7 months ago
2008
IEEE
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
DAC
2010
ACM
13 years 10 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...