: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Numerical design optimization algorithms are highly sensitive to the particular formulation of the optimization problems they are given. The formulation of the search space, the o...
Thomas Ellman, John Keane, Takahiro Murata, Mark S...