1016 search results - page 117 / 204 » Test Generation for Designs with On-Chip Clock Generators |
144
Voted
VLSID
2000
IEEE
15 years 7 months ago
2000
IEEE
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
125
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ISQED
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
142
Voted
VLSID
2001
IEEE
16 years 4 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
168
Voted
NOCS
2008
IEEE
15 years 10 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
154
Voted
CF
2005
ACM
15 years 5 months ago
2005
ACM
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...