1016 search results - page 25 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
IJNSEC
2010
13 years 2 months ago
2010
Chaotic systems have many interesting features such as sensitivity on initial condition and system parameter, ergodicity and mixing properties. In this paper, we exploit these int...
DATE
2010
IEEE
13 years 12 months ago
2010
IEEE
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Static Linked Faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and m...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...