1016 search results - page 30 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
ET
2002
13 years 7 months ago
2002
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
VLSID
1997
IEEE
13 years 12 months ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...