1016 search results - page 34 / 204 » Test Generation for Designs with On-Chip Clock Generators |
OOPSLA
2005
Springer
14 years 1 months ago
2005
Springer
Designing component-based application that meets performance requirements remains a challenging problem, and usually requires a prototype to be constructed to benchmark performanc...
ERSA
2009
13 years 5 months ago
2009
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
ITC
2003
IEEE
14 years 28 days ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...