1016 search results - page 4 / 204 » Test Generation for Designs with On-Chip Clock Generators |
140
Voted
GLVLSI
1998
IEEE
15 years 7 months ago
1998
IEEE
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
149
click to vote
PATMOS
2000
Springer
15 years 7 months ago
2000
Springer
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
138
Voted
DAC
2000
ACM
16 years 4 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
125
click to vote
MSE
2003
IEEE
15 years 8 months ago
2003
IEEE
A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Intern...
130
Voted
FDL
2005
IEEE
15 years 9 months ago
2005
IEEE
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...