1016 search results - page 64 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ASWEC
2004
IEEE
13 years 11 months ago
2004
IEEE
Assessing the likely run-time performance of applications using thin-client architectures during their design is very difficult. We describe SoftArch/Thin, a thin-client test-bed ...
ICMCS
2005
IEEE
14 years 1 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
IPPS
1998
IEEE
14 years 6 hour ago
1998
IEEE
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
ISMVL
2007
IEEE
14 years 2 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
AWCC
2004
Springer
14 years 1 months ago
2004
Springer
This paper proposes progressive group testing techniques to test large number of Web services (WS) available on Internet. At the unit testing level, the WS with the same functional...