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» Test Generation for Designs with On-Chip Clock Generators
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VTS
1995
IEEE
100views Hardware» more  VTS 1995»
13 years 11 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
DAC
2002
ACM
14 years 8 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...
RTSS
1998
IEEE
14 years 12 hour ago
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
Inki Hong, Gang Qu, Miodrag Potkonjak, Mani B. Sri...
COMPUTER
2002
75views more  COMPUTER 2002»
13 years 7 months ago
GUI Testing: Pitfalls and Process
ion, so mapping between GUI events and the underlying code is not straightforward. Code-based coverage criteria do not necessarily address problematic interactions between the GUI&...
Atif M. Memon
DAC
2011
ACM
12 years 7 months ago
Synchronous sequential computation with molecular reactions
Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit vo...
Hua Jiang, Marc D. Riedel, Keshab K. Parhi