145 search results - page 8 / 29 » Test Resource Partitioning and Optimization for SOC Designs |
DSD
2006
IEEE
14 years 8 days ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
ET
2002
13 years 8 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
DSD
2005
IEEE
14 years 2 months ago
2005
IEEE
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
MTDT
2003
IEEE
14 years 1 months ago
2003
IEEE
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...