We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
Anshuman Chandra, Krishnendu Chakrabarty, Rafael A...
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...