67 search results - page 1 / 14 » Test Resource Partitioning and Reduced Pin-Count Testing Bas... |
DATE
2002
IEEE
14 years 15 days ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...
VTS
2002
IEEE
14 years 13 days ago
2002
IEEE
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
ET
2002
13 years 7 months ago
2002
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...