18 search results - page 2 / 4 » Test Time Reduction Reusing Multiple Processors in a Network... |
RSP
2003
IEEE
14 years 5 days ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
ISQED
2006
IEEE
14 years 28 days ago
2006
IEEE
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
VLSID
2008
IEEE
14 years 7 months ago
2008
IEEE
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...