142 search results - page 13 / 29 » Test architecture design and optimization for three-dimensio... |
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
DAC
2012
ACM
11 years 11 months ago
2012
ACM
Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a d...
CORR
2007
Springer
13 years 8 months ago
2007
Springer
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
DAC
2010
ACM
13 years 12 months ago
2010
ACM
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
CASES
2001
ACM
14 years 7 days ago
2001
ACM
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...