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ENGL
2007
180views more  ENGL 2007»
13 years 7 months ago
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
K. Paramasivam, K. Gunavathi
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
14 years 1 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
VLSID
2007
IEEE
94views VLSI» more  VLSID 2007»
14 years 8 months ago
A Reduced Complexity Algorithm for Minimizing N-Detect Tests
? We give a new recursive rounding linear programming (LP) solution to the problem of N-detect test minimzation. This is a polynomialtime solution that closely approximates the exa...
Kalyana R. Kantipudi, Vishwani D. Agrawal
DATE
2006
IEEE
73views Hardware» more  DATE 2006»
14 years 1 months ago
Minimizing test power in SRAM through reduction of pre-charge activity
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hash...
DAC
1997
ACM
13 years 12 months ago
ATPG for Heat Dissipation Minimization During Scan Testing
An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of l...
Seongmoon Wang, Sandeep K. Gupta