112 search results - page 16 / 23 » Test generation in VLSI circuits for crosstalk noise |
DFT
2002
IEEE
14 years 18 days ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
IOLTS
2000
IEEE
14 years 23 hour ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...