112 search results - page 18 / 23 » Test generation in VLSI circuits for crosstalk noise |
VTS
2002
IEEE
14 years 16 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
VLSID
1996
IEEE
13 years 11 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
TVLSI
1998
13 years 7 months ago
1998
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efï...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurement...