502 search results - page 7 / 101 » Test pattern generation based on arithmetic operations |
ASPDAC
1998
ACM
14 years 2 months ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
ET
2000
13 years 9 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
EURODAC
1990
IEEE
14 years 1 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
ITC
1996
IEEE
14 years 1 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
EVOW
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. This work presents scale invariant region detectors that apply evolved operators to extract an interest measure. We evaluate operators using their repeatability rate, and...