64 search results - page 4 / 13 » Test pattern generation for width compression in BIST |
TC
2008
13 years 7 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
ATS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
ATS
1998
IEEE
13 years 11 months ago
1998
IEEE
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE