72 search results - page 1 / 15 » Test register insertion with minimum hardware cost |
ICCAD
1995
IEEE
14 years 2 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
ISPD
2004
ACM
14 years 4 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ASPDAC
2004
ACM
14 years 4 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
ISCAS
1995
IEEE
14 years 2 months ago
1995
IEEE
: Configurations of adders and registers, which are available in tnany datapaths, can be utilized to generate pattems and to compact test responses. Thispaper unalyzes tlie patiern...