72 search results - page 3 / 15 » Test register insertion with minimum hardware cost |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
ISPD
2004
ACM
14 years 26 days ago
2004
ACM
VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, i...
ISQED
2002
IEEE
14 years 11 days ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
VTS
2002
IEEE
14 years 10 days ago
2002
IEEE
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...