72 search results - page 8 / 15 » Test register insertion with minimum hardware cost |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to ou...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical planarization (CMP) to remove excess of deposited oxide and attain a planar...
WEA
2005
Springer
14 years 28 days ago
2005
Springer
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...