72 search results - page 9 / 15 » Test register insertion with minimum hardware cost |
ISSS
2002
IEEE
14 years 11 days ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
DELTA
2008
IEEE
14 years 1 months ago
2008
IEEE
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
FPL
1997
Springer
13 years 11 months ago
1997
Springer
Technology mapping can be viewed as the optimization problem of finding a minimum cost cover of the given Boolean network by choosing from given library of logic cells. The core of...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...