624 search results - page 1 / 125 » Test set compaction algorithms for combinational circuits |
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
EURODAC
1995
IEEE
13 years 10 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICCAD
2001
IEEE
14 years 3 months ago
2001
IEEE
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...
ASPDAC
2006
ACM
14 years 29 days ago
2006
ACM
Abstract— Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored...