624 search results - page 4 / 125 » Test set compaction algorithms for combinational circuits |
ICCAD
2009
IEEE
13 years 4 months ago
2009
IEEE
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
ATS
2000
IEEE
13 years 11 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
ATS
1996
IEEE
13 years 11 months ago
1996
IEEE
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...