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EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
14 years 2 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
SAC
2006
ACM
13 years 11 months ago
A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences
The objective of testing is to determine the conformance between a system and its specification. When testing distributed systems, the existence of multiple testers brings out the...
Kai Chen, Fan Jiang, Chuan-dong Huang
HASE
2008
IEEE
14 years 5 months ago
An Interaction-Based Test Sequence Generation Approach for Testing Web Applications
Web applications often use dynamic pages that interact with each other by accessing shared objects, e.g., session objects. Interactions between dynamic pages need to be carefully ...
Wenhua Wang, Sreedevi Sampath, Yu Lei, Raghu Kacke...
EVOW
1999
Springer
14 years 3 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...