244 search results - page 16 / 49 » Testing Digital Circuits with Constraints |
DATE
1999
IEEE
14 years 28 days ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
ITC
2000
IEEE
14 years 1 months ago
2000
IEEE
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
ICES
2000
Springer
14 years 6 days ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ETS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete ...