244 search results - page 23 / 49 » Testing Digital Circuits with Constraints |
DATE
2010
IEEE
14 years 8 days ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
CHARME
1995
Springer
14 years 1 months ago
1995
Springer
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
CORR
2006
Springer
13 years 10 months ago
2006
Springer
The asynchronous systems f are the models of the asynchronous circuits from digital electrical engineering. They are multi-valued functions that associate to each input u : R {0, ...
ICNC
2005
Springer
14 years 3 months ago
2005
Springer
Abstract. In this paper we propose a procedure for the storage and retrieval of digital signals utilizing DNA. Digital signals are encoded in DNA sequences that satisfy among other...