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» Testing Digital Circuits with Constraints
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ATS
2003
IEEE
131views Hardware» more  ATS 2003»
14 years 3 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 2 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
DAC
2004
ACM
14 years 10 months ago
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
Chong Zhao, Xiaoliang Bai, Sujit Dey
ISTCS
1993
Springer
14 years 1 months ago
Analog Computation Via Neural Networks
We pursue a particular approach to analog computation, based on dynamical systems of the type used in neural networks research. Our systems have a xed structure, invariant in time...
Hava T. Siegelmann, Eduardo D. Sontag
ICES
2005
Springer
177views Hardware» more  ICES 2005»
14 years 3 months ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez