244 search results - page 4 / 49 » Testing Digital Circuits with Constraints |
ATS
1997
IEEE
14 years 24 days ago
1997
IEEE
SAC
1997
ACM
14 years 4 days ago
1997
ACM
ICTAI
1994
IEEE
14 years 3 days ago
1994
IEEE
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
GECCO
2000
Springer
14 years 6 days ago
2000
Springer
This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits correspondi...