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DSD
2007
IEEE
119views Hardware» more  DSD 2007»
14 years 3 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...
IOLTS
2000
IEEE
84views Hardware» more  IOLTS 2000»
14 years 1 months ago
Self-Testing of FPGA Delay Faults in the System Environment
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
Andrzej Krasniewski
ICFEM
2005
Springer
14 years 2 months ago
Testing Real-Time Multi Input-Output Systems
Abstract. In formal testing, the assumption of input enabling is typically made. This assumption requires all inputs to be enabled anytime. In addition, the useful concept of quies...
Laura Brandán Briones, Ed Brinksma
FATES
2004
Springer
14 years 2 months ago
Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach
A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or ...
Behzad Bordbar, Kozo Okano
CIBSE
2008
ACM
13 years 11 months ago
Using Refinement Checking as System Testing
Abstract. Software testing is an expensive and time-consuming activity; it is also error-prone due to human factors. But, it still is the most common effort used in the software in...
Cristiano Bertolini, Alexandre Mota