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ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
14 years 3 months ago
A dynamic test compaction procedure for high-quality path delay testing
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, T...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
14 years 2 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
XPU
2004
Springer
14 years 3 months ago
Putting a Motor on the Canoo WebTest Acceptance Testing Framework
Abstract. User acceptance testing is finally getting the attention and tool support it deserves. It is imperative that acceptance tests follow the best practices and embody the cri...
Jennitta Andrea
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
14 years 2 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
14 years 2 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel