1610 search results - page 16 / 322 » Testing Patterns |
ATS
2009
IEEE
14 years 4 months ago
2009
IEEE
Power distribution network (PDN) designs for today’s high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and henc...
EURODAC
1994
IEEE
14 years 2 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
CONSTRAINTS
2007
13 years 10 months ago
2007
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
ET
2002
13 years 9 months ago
2002
The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test ar...
DATE
2004
IEEE
14 years 1 months ago
2004
IEEE
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...