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DATE
2000
IEEE
139views Hardware» more  DATE 2000»
14 years 2 months ago
A VHDL Error Simulator for Functional Test Generation
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
Alessandro Fin, Franco Fummi
ICST
2008
IEEE
14 years 4 months ago
Testing Consequences of Grime Buildup in Object Oriented Design Patterns
Evidence suggests that as software ages the original realizations of design patterns remain in place, and participants in design pattern realizations accumulate “grime” – no...
Clemente Izurieta, James M. Bieman
OOPSLA
2005
Springer
14 years 3 months ago
Improving architecture testability with patterns
There is a critical need for approaches to support software testing. Our research exploits the information described at Architectural Patterns to drive the definition of tests. As...
Roberta Coelho, Uirá Kulesza, Arndt von Sta...
DATE
2009
IEEE
94views Hardware» more  DATE 2009»
14 years 4 months ago
Improving compressed test pattern generation for multiple scan chain failure diagnosis
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
IOLTS
2007
IEEE
120views Hardware» more  IOLTS 2007»
14 years 4 months ago
Accelerating Soft Error Rate Testing Through Pattern Selection
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu