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DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 4 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito
ACL
2006
13 years 11 months ago
A Rote Extractor with Edit Distance-Based Generalisation and Multi-Corpora Precision Calculation
In this paper, we describe a rote extractor that learns patterns for finding semantic relationships in unrestricted text, with new procedures for pattern generalization and scorin...
Enrique Alfonseca, Pablo Castells, Manabu Okumura,...
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 2 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
14 years 3 months ago
Power-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
Mehrdad Nourani, James Chin
VTS
2002
IEEE
107views Hardware» more  VTS 2002»
14 years 2 months ago
Testing High-Speed SoCs Using Low-Speed ATEs
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
Mehrdad Nourani, James Chin