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XPU
2004
Springer
14 years 3 months ago
Generative Acceptance Testing for Difficult-to-Test Software
Abstract. While there are many excellent acceptance testing tools and frameworks available today, this paper presents an alternative approach, involving generating code from tests ...
Jennitta Andrea
ICCD
2004
IEEE
132views Hardware» more  ICCD 2004»
14 years 7 months ago
Compressed Embedded Diagnosis of Logic Cores
This paper introduces a new method for deterministic diagnosis of logic cores. The proposed method is based on onchip decompression and comparison of incompletely specified test ...
Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 4 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
14 years 2 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
ATS
2003
IEEE
105views Hardware» more  ATS 2003»
14 years 3 months ago
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...