1610 search results - page 53 / 322 » Testing Patterns |
ICCD
2003
IEEE
14 years 3 months ago
2003
IEEE
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
ATS
1997
IEEE
14 years 2 months ago
1997
IEEE
This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at fault models. In the first part, we prese...
ET
2006
13 years 10 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
RSP
1998
IEEE
14 years 2 months ago
1998
IEEE
The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newl...