: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
This paper presents a tutorial on mixed-signal testing. Our focus is on testing the analog portion of the mixed-signal device, as the digital portion is handled in the usual way. ...
Test generation and execution are often hampered by the large state spaces of the systems involved. In automata (or transition system) based test algorithms, taking advantage of s...
Abstract--We adapt methods originally developed in information and coding theory to solve some testing problems. The efficiency of two-stage pool testing of items is characterized ...