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DATE
2003
IEEE
105views Hardware» more  DATE 2003»
14 years 1 months ago
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
14 years 15 days ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
ICCAD
1996
IEEE
103views Hardware» more  ICCAD 1996»
14 years 11 days ago
Metrics, techniques and recent developments in mixed-signal testing
This paper presents a tutorial on mixed-signal testing. Our focus is on testing the analog portion of the mixed-signal device, as the digital portion is handled in the usual way. ...
Gordon W. Roberts
FORTE
1998
13 years 9 months ago
Exploiting Symmetry in Protocol Testing
Test generation and execution are often hampered by the large state spaces of the systems involved. In automata (or transition system) based test algorithms, taking advantage of s...
Judi Romijn, Jan Springintveld
TIT
2002
102views more  TIT 2002»
13 years 7 months ago
Asymptotic efficiency of two-stage disjunctive testing
Abstract--We adapt methods originally developed in information and coding theory to solve some testing problems. The efficiency of two-stage pool testing of items is characterized ...
Toby Berger, Vladimir I. Levenshtein