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DATE
2007
IEEE
83views Hardware» more  DATE 2007»
14 years 2 months ago
High-level test synthesis for delay fault testability
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Sying-Jyan Wang, Tung-Hua Yeh
APSEC
2006
IEEE
14 years 2 months ago
Testing of Timer Function Blocks in FBD
Testing for time-related behaviors of PLC software is important and should be performed carefully. We propose a structural testing technique on Function Block Diagram(FBD) network...
Eunkyoung Jee, Seungjae Jeon, Hojung Bang, Sung De...
RSP
2003
IEEE
117views Control Systems» more  RSP 2003»
14 years 1 months ago
Prototype-Based Tests for Hybrid Reactive Systems
Model-based testing relies on the use of behavior models to automatically generate sequences of inputs and expected outputs. These sequences can be used as test cases to the end o...
Gabor Hahn, Jan Philipps, Alexander Pretschner, Th...
SIGSOFT
2006
ACM
14 years 2 months ago
Simulation-based test adequacy criteria for distributed systems
Developers of distributed systems routinely construct discrete-event simulations to help understand and evaluate the behavior of inter-component protocols. Simulations are abstrac...
Matthew J. Rutherford, Antonio Carzaniga, Alexande...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 1 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt