A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Testing for time-related behaviors of PLC software is important and should be performed carefully. We propose a structural testing technique on Function Block Diagram(FBD) network...
Model-based testing relies on the use of behavior models to automatically generate sequences of inputs and expected outputs. These sequences can be used as test cases to the end o...
Gabor Hahn, Jan Philipps, Alexander Pretschner, Th...
Developers of distributed systems routinely construct discrete-event simulations to help understand and evaluate the behavior of inter-component protocols. Simulations are abstrac...
Matthew J. Rutherford, Antonio Carzaniga, Alexande...
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...