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ATS
1998
IEEE
91views Hardware» more  ATS 1998»
14 years 11 days ago
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...
VTS
1996
IEEE
112views Hardware» more  VTS 1996»
14 years 7 days ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
AMAST
2006
Springer
13 years 12 months ago
Testing Semantics: Connecting Processes and Process Logics
We propose a methodology based on testing as a framework to capture the interactions of a machine represented in a denotational model and the data it manipulates. Using a duality t...
Dusko Pavlovic, Michael W. Mislove, James Worrell
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 12 months ago
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
Mounir Benabdenbi, Alain Greiner, François ...
EMSOFT
2006
Springer
13 years 11 months ago
Software partitioning for effective automated unit testing
A key problem for effective unit testing is the difficulty of partitioning large software systems into appropriate units that can be tested in isolation. We present an approach th...
Arindam Chakrabarti, Patrice Godefroid