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» Testing embedded-core based system chips
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DFT
2003
IEEE
120views VLSI» more  DFT 2003»
14 years 1 months ago
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Che...
GLVLSI
2008
IEEE
183views VLSI» more  GLVLSI 2008»
13 years 9 months ago
An analytical model for the upper bound on temperature differences on a chip
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be u...
Shervin Sharifi, Tajana Simunic Rosing
DFT
2005
IEEE
126views VLSI» more  DFT 2005»
14 years 2 months ago
Analysis and Testing for Error Tolerant Motion Estimation
We propose a novel system-level error tolerance approach specifically targeted for multimedia compression algorithms. In particular we focus on the motion estimation process perf...
Hyukjune Chung, Antonio Ortega
KDD
2000
ACM
211views Data Mining» more  KDD 2000»
14 years 2 days ago
Mining IC test data to optimize VLSI testing
We describe an application of data mining and decision analysis to the problem of die-level functional test in integrated circuit manufacturing. Integrated circuits are fabricated...
Tony Fountain, Thomas G. Dietterich, Bill Sudyka
JIPS
2007
88views more  JIPS 2007»
13 years 8 months ago
Interface Development for the Point-of-care device based on SOPC
: This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed POC device comprises an ARM9 embedded processor and...
Hong Bum Son, Sung Gun Song, Jae Wook Jung, Chang ...