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DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 2 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
CP
2007
Springer
14 years 1 months ago
Exploring Different Constraint-Based Modelings for Program Verification
Recently, constraint-programming techniques have been used to generate test data and to verify the conformity of a program with its specification. Constraint generated for these ta...
Hélène Collavizza, Michel Rueher
ISSRE
2003
IEEE
14 years 2 months ago
Requirements by Contracts allow Automated System Testing
Use-cases and scenarios have been identified as good inputs to generate test cases and oracles at requirement level. Yet to have an automated generation, information is missing f...
Clémentine Nebut, Franck Fleurey, Yves Le T...
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
14 years 2 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
MTDT
2000
IEEE
137views Hardware» more  MTDT 2000»
14 years 2 months ago
Diagnostic Testing of Embedded Memories Based on Output Tracing
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Red...