709 search results - page 130 / 142 » Texture segmentation benchmark |
FPGA
2005
ACM
14 years 3 months ago
2005
ACM
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
FPGA
2004
ACM
14 years 3 months ago
2004
ACM
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...
SRDS
2003
IEEE
14 years 3 months ago
2003
IEEE
Group communication protocols constitute a basic building block for highly dependable distributed applications. Designing and correctly implementing a group communication system (...
EMMCVPR
2001
Springer
14 years 2 months ago
2001
Springer
After [15, 31, 19, 8, 25, 5] minimum cut/maximum flow algorithms on graphs emerged as an increasingly useful tool for exact or approximate energy minimization in low-level vision...