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DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 2 months ago
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
Isabelle Puaut, Christophe Pais
ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
13 years 6 days ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
PCI
2005
Springer
14 years 2 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
CODES
2010
IEEE
13 years 6 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
PERCOM
2010
ACM
13 years 7 months ago
Embedding Semantic Product Memories in the web of things
—Today, RFID is used to identify a wide range of work pieces or individual products for tracking their movements through the logistics chain. For future purposes the idea of stor...
Christian Seitz, Christoph Legat, Jörg Neidig