DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
In this paper we present an extension to an existing hash based packet classification technique in order to improve its performance in a distributed network access control environm...
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
An infrastructure for remote instrument access, data acquisition and data management is being developed for e-Research. The Common Instrument Middleware Architecture (CIMA) is bei...
Ian M. Atkinson, Douglas du Boulay, Clinton Chee, ...
This paper presents the mechanisms proposed by a generic cognitive architecture for virtual characters with emotional influenced behaviors, called cognitiva, to maintain behavior ...