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ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
14 years 1 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
NETWORKING
2004
13 years 10 months ago
Improving Distributed Firewalls Performance through Vertical Load Balancing
In this paper we present an extension to an existing hash based packet classification technique in order to improve its performance in a distributed network access control environm...
Olivier Paul
DAC
2001
ACM
14 years 9 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
ACSW
2007
13 years 10 months ago
Developing CIMA-Based Cyberinfrastructure for Remote Access to Scientific Instruments and Collaborative e-Research
An infrastructure for remote instrument access, data acquisition and data management is being developed for e-Research. The Common Instrument Middleware Architecture (CIMA) is bei...
Ian M. Atkinson, Douglas du Boulay, Clinton Chee, ...
STORYTELLING
2005
Springer
14 years 2 months ago
An Emotional Architecture for Virtual Characters
This paper presents the mechanisms proposed by a generic cognitive architecture for virtual characters with emotional influenced behaviors, called cognitiva, to maintain behavior ...
Ricardo Imbert, Angélica de Antonio